Key Responsibilities Include But Not Limited To
- Innovate and own Architecture, Design and Development of high performance, low power IO PHY meeting latest Memory Industry Standards for LPDDR, DDR Or Proprietary On-Package Interconnects standards
- Owns PHY level Architecture study and recommends design trade-off aligned to IP/SoC requirement and roadmap
- Collaborate across functional teams - Logic, Circuit, Verification, Structural Design in PHY level definition meeting Best In Class Power, Performance and Area metrics
- Collaborate with SoC integration teams on PHY level requirement and integration issues
- Mentor and develop technical leadership pipeline.
- Experience in Circuit u-Architecture definition of High Speed Memory Interfaces example DDR, LPDDR, GDDR, or On-Package Interconnect IO interfaces, Ultra Low Power Die-to-Die IO, PCIe, Serdes. Design achieved production in high volume and extensive exposure on post-silicon debug and BIOS based PHY training algorithm
- Experience in high speed custom building blocks for High Speed Interfaces, RTL logic design, Synthesis, Physical design, Power analysis and/or integration aspects for IO PHY in SoC
- Good Understanding of LPDDR/DDR JEDEC specifications and related DDR Protocols
- Good understanding of design for yield and exposure to production challenges in latest technology process node
- Cross-discipline knowledge in any of these areas, such as Analog integration, RTL/System Verilog, Static timing analysis concepts, APR, Floor-planning, Metal-routing, Power-grid, Memory IO training MRC and HAS/MAS specification documentation.
- Strong written and oral communication skills
- BSEE with 15+ years relevant experience or Master's with 10+ years relevant experience required.